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INTEGRATED CIRCUITS
DATA SHEET
OQ8868 Digital Servo Integrated Circuit Silent (DSICS)
Product specification Supersedes data of 1996 Apr 11 File under Integrated Circuits, IC01 1997 Feb 12
Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
FEATURES The DSICS realizes the following servo functions: * Focus servo loop * Radial servo loop * Built-in access procedure * Sledge motor servo loop * Three line (TDA1301T-like; same on hardware level, coefficients differ) or I2C-bus serial interface with system controller. Other features are: * Single supply voltage (5 V) * Flexible system oscillator * Usable for single/double Foucault and astigmatic focus * Wide range of adjustable servo characteristics possible * Automatic focus start-up procedure and in-lock indication * Fast focus restart procedure * Sophisticated track loss detection mechanism * Extended radial error signal * Automatic initialization and jump procedure for radial servo * Automatic radial error gain and offset control * Sophisticated defect detector * Shock detector * Fast serial communication * Low noise servo loops * Automatic gain control for the complete focus and radial loop * Fast track counting signal input * Steered sledge jump * Radial actuator damping. Features that improve on its predecessor, the TDA1301T: * Low noise in the focus loop * Faster serial communication * Improved jump performance. ORDERING INFORMATION TYPE NUMBER OQ8868 PACKAGE NAME QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm 2 Added features are: * High level watchdogs
OQ8868
* Decoder (LO9585, LO9588 or HD60) communication support * Application debugging support * Pulsed sledge mode * Auto gain control on radial and focus loop * I2C-bus serial communication * Externally available defect detector signals. GENERAL DESCRIPTION The Digital Servo Integrated Circuit Silent (DSICS) IC provides all servo functions except the spindle motor control in two-stage Compact Disc (CD) systems. It offers a high degree of integration, combined with the low additional cost of external components. The servo characteristics are widely adjustable by means of a three-wire serial interface, which offers great flexibility for the application of different CD mechanisms. The servo chip accepts diode currents and drives various power stages. Proper functioning of the focus and radial AGCs requires a digital power stage (SZA1010). It can drive normal, CDM12-like, mechanisms. It is the improved version of its predecessor, the DSIC2 (TDA1301).
VERSION SOT307-2
1997 Feb 12
Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
QUICK REFERENCE DATA SYMBOL VDDD VDDA IDDD IDD(q) IDDA II PARAMETER digital supply voltage analog supply voltage digital supply current digital quiescent supply current analog supply current input current for pins D1 to D4 for pins S1 and S2 Ptot Tamb Notes 1. Maximum input range varies from 3.8 to 12 A and varies with the reference current through XTLR. 2. Maximum input range varies from 1.9 to 6 A and varies with the reference current through XTLR. total power dissipation operating ambient temperature note 1 note 2 - - - -40 - - 115 - 12 6 - +85 CONDITIONS MIN. 4.5 4.5 - - - - - 17 - 5 TYP.
OQ8868
MAX. 5.5 5.5 - 10 - V V
UNIT
mA A mA A A mW C
1997 Feb 12
3
Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
BLOCK DIAGRAM
OQ8868
handbook, full pagewidth
VDDD3 18 17 16 19 15 38 11 3 ANALOG-TO-DIGITAL CONVERTER COMM 30
VDDD1 40 25 26 24 DA CDID RAB
SIDA/SDA SICL/SCL SILD ENIIC RSTI FTC VDDA D1
NS
33
SL
NS
32
FO
NS D2 4 ANALOG-TO-DIGITAL CONVERTER
31
RA
35 D3 5 ANALOG-TO-DIGITAL CONVERTER CONTROL MONITOR 36 37
RP TL FOK
D4
7
ANALOG-TO-DIGITAL CONVERTER
43 27
LDO RSTO
S1
8
ANALOG-TO-DIGITAL CONVERTER
S2
9
ANALOG-TO-DIGITAL CONVERTER
XTLR VSSA DEFI VrefH VrefL
12 10 41 2 6
ANALOG-TO-DIGITAL CONVERTER 14 ERROR DETECTION REFERENCE 20 42 OTD INTREQ DEFO
XTALO XTALI
22 21 OSCILLATOR
28
CLKO
TEST1 TEST2
1 44 TEST
OQ8868
39 34 29 23 13
MGE335
VSSD1 VSSD2 VSSD3 VSSD4 VSSD5
Fig.1 Block diagram.
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Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
PINNING SYMBOL TEST1 VrefH D1 D2 D3 VrefL D4 S1 S2 VSSA VDDA XTLR VSSD5 OTD RSTI SILD SICL/SCL SIDA/SDA ENIIC INTREQ XTALI XTALO VSSD4 RAB DA CDIC RSTO CLKO VSSD3 VDDD3 RA FO SL VSSD2 RP TL FOK FTC VSSD1 VDDD1 1997 Feb 12 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DESCRIPTION test input 1 (LOW for normal operation); internal pull-down high reference for A/D converter (input) unipolar current input (central diode signal input) unipolar current input (central diode signal input) unipolar current input (central diode signal input) low reference for A/D converter (input) unipolar current input (central diode signal input) unipolar current input (central diode signal input) unipolar current input (central diode signal input) analog ground analog supply voltage reference current input digital ground 5 off track detector (output) reset input (active HIGH) serial host interface load serial host interface clock /I2C-bus clock (SCL) serial host interface data /I2C-bus data (SDA) enable I2C-bus serial format (active LOW) interrupt request output (active LOW) oscillator input oscillator output digital ground 4 serial decoder interface load (output) serial decoder interface data (input/output) serial decoder interface clock (output) reset output (active LOW) clock buffer output digital ground 3 digital supply voltage 3 radial actuator output focus actuator output sledge output digital ground 2 radial polarity signal track loss signal focus OK output fast track counting input (internal pull-down) digital ground digital supply voltage 1 5
OQ8868
Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
SYMBOL DEFI DEFO LDO TEST2 PIN 41 42 43 44 defect detector output laser drive on output (open drain, active LOW) test input 2 (low for normal operation) DESCRIPTION defect detector input (connected to DEFO)
OQ8868
40 VDDD1
42 DEFO
41 DEFI
handbook, full pagewidth
34 VSSD2
39 VSSD1
44 TEST2
37 FOK
43 LDO
38 FTC
35 RP
36 TL
TEST1 VrefH D1 D2 D3 VrefL D4 S1 S2
1 2 3 4 5 6 7 8 9
33 SL 32 FO 31 RA 30 VDDD3 29 VSSD3
OQ8868
28 CLKO 27 RSTO 26 CDIC 25 DA 24 RAB 23 VSSD4
VSSA 10 VDDA 11
XTALI 21
VSSD5 13
SICL/SCL 17
SIDA/SDA 18
INTREQ 20
XTALO 22
XTLR 12
OTD 14
RSTI 15
SILD 16
ENIIC 19
MGE334
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION Servo input circuits This IC has been designed for Compact Disc drives for audio and data applications and uses diode currents as input signals. The analog signals from the diode pre-processor are converted into a digital representation using analog-to-digital (A/D) converters.
Signal conditioning The digital codes retrieved from the A/D converters are connected to a logic circuit, to obtain the various control signals. The signals from the central aperture detectors are processed in such a way that the following normalized focus error signal is generated: D1 - D2 D3 - D4 FE n = --------------------- - --------------------D1 + D2 D3 + D4 where the detector set-up is assumed as shown in Fig.3.
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Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
OQ8868
handbook, halfpage
SATELLITE DIODE R1
SATELLITE DIODE R1
SATELLITE DIODE R1
D1 D3 D2
D2 D4
D1 D3
D1 D2 D3 D4
SATELLITE DIODE R2 single Foucault
SATELLITE DIODE R2 astigmatic focus
SATELLITE DIODE R2 double Foucault
MGE336
Fig.3 Detector arrangement.
For the single Foucault focusing method, the DSICS signal conditioning can be switched under software control so that the signal processing is as follows: D1 - D2 FE n = 2 x --------------------D1 + D2 The FEn thus obtained is further processed by a Proportional Integral and Differential (PID) filter section. A focus OK (FOK) flag is generated by means of the central aperture signal and an adjustable reference level. This signal is used to provide extra protection for the TL generation, and also for the focus start-up procedure and the drop-out detection. The radial or tracking error signal is generated by means of the satellite detector signals S1and S2. The radial error signal can be formulated as follows: REs = (S1 - S2) x RE_gain + (S1 + S2) - RE_offset where the index `s' indicates the automatic scaling operation that is performed on the radial error signal. This scaling is necessary to avoid non-optimum dynamic range usage in the digital representation and reduces radial bandwidth spread. Furthermore, the radial error signal will be made free from offset during start-up of the disc. The four signals from the central aperture detectors, together with the satellite detector signals, generate a track position indication (TPI) signal. This can be formulated as follows: TPI = sign[(D1 + D2 + D3 + D4) - (S1 + S2) x Sum_gain] where the weighting factor Sum_gain is generated internally in the DSICS during initialization. 1997 Feb 12 7
Servo output circuits The Off Track Detection (OTD) signal indicates an off track situation. The polarity of this signal is programmable. During active radial tracking, OTD is realized by continuously monitoring the off track counter value. The off track flag becomes valid whenever the off track counter value is not equal to zero. Depending on the type of extended S-curve, the off track counter is reset after 3 extend or at the original track in the 21 track extend 4 4 mode. The control signals for the different actuators (FO, RA and SL) are 1-bit noise-shaped digital outputs at 1.0584 MHz (DSD mode). At 2.1168 MHz, noise-shaped signals can also be selected. An analog representation of the output signals can be achieved by connecting a first-order low-pass filter to the outputs. Focus control The DSICS digital controller includes the following focus servo functions: 1. Focus start-up 2. Focus position control loop 3. Dropout detection 4. Focus loss detection and fast restart 5. Focus loop gain switching 6. Focus automatic gain control loop.
Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
FOCUS START-UP Five initially-loaded coefficients influence the start-up behaviour of the focus controller. The automatically generated triangle voltage can be influenced by three parameters for the height (ramp_height) and DC-offset (ramp_offset) of the triangle and its steepness (ramp_inc). For protection against false focus point detections, two parameters are available, these being an absolute level on the CA signal (CA_start) and a level on the FEn signal (FE_start). When this CA level is reached, the FOK signal becomes true. If this FOK signal is true and the level on the FEn signal is reached, the focus PID is enabled to switch on when the next zero crossing is detected in the FEn signal. FOCUS POSITION CONTROL LOOP The focus control loop contains a digital PID controller, which has five parameters available to the user. These coefficients influence the integrating (foc_int), proportional (foc_prop) and differentiating (foc_pole_lead) action of this PID and a digital low-pass filter (foc_pole_noise) following the PID. The fifth coefficient (foc_gain) influences the loop gain. DROPOUT DETECTION This detector can be influenced by one parameter (CA_drop). The FOK signal will become false and the PID integrator will hold if the CA signal drops below this programmable absolute CA level. When the FOK signal becomes false, it is assumed initially that this is caused by a black dot. FOCUS LOSS DETECTION AND FAST RESTART Whenever FOK is false for longer than approximately 3 ms, it is assumed that the focus point is lost. A fast restart procedure is initiated, which is capable of restarting the focus loop within 200 to 300 ms, depending on the microprocessor-programmed coefficients. FOCUS LOOP GAIN SWITCHING The gain of the focus control loop (foc_gain) can be multiplied by a factor of 2 or divided by 2 during normal operation. The integrator value of the PID is corrected accordingly. The differentiating (foc_pole_lead) action of the PID can be switched at the same time when gain switching is performed. FOCUS AUTOMATIC GAIN CONTROL LOOP
OQ8868
The loop gain of the focus control loop can be corrected automatically to eliminate tolerances in the focus loop. This gain control injects a signal into the loop that is used to correct the loop gain. Since this decreases the optimum performance, the gain control should only be activated briefly, e.g. when starting a new disc. Radial control The DSICS digital controller includes the following radial servo functions: 1. Level initialization 2. Sledge home 3. Tracking control 4. Access 5. Radial automatic gain control loop. LEVEL INITIALIZATION During start-up, an automatic adjustment procedure is activated, to set the values of the radial error gain (RE_gain), offset (RE_offset) and satellite sum signal gain (Sum_gain) for TPI level generation. The initialization procedure runs in a radial open loop situation and is 300 ms. This start-up time period may coincide with the last part of the turntable motor start-up time period. Automatic gain adjustment: As a result of this initialization, the amplitude of the RE signal is adjusted within 10% around the nominal RE amplitude. Offset adjustment: The additional offset in RE due to the limited accuracy of the start-up procedure is less than 50 nm. TPI level generation: The accuracy of the initialization procedure is such that the duty cycle range of TPI becomes 0.4 < duty cycle < 0.6. Duty cycle definition: TPI-HIGH/TPI-period). SLEDGE HOME The sledge moves to a reference position (end_stop_switch) at the inner side of the disc with user-defined voltage.
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Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
TRACKING CONTROL The actuator is controlled using a PID loop filter with user-defined coefficients and gain. For stable operation between the tracks, the S-curve is extended over 34 track. Upon a request from the microprocessor, S-curve extension over 214 tracks is used, automatically changing to access control when exceeding those 214 tracks. Both modes of S-curve extension make use of a track-count mechanism, as described in section "Off track counting". In this mode, track counting results in automatic `return to zero track', to avoid major music rhythm disturbances in the audio output for improved shock resistance. The sledge is continuously controlled using the filtered value of the integrator contents of the actuator, or upon request by the microprocessor. The microprocessor can read out this integrator value and provides the sledge with step pulses to reduce power consumption. Filter coefficients of the continuous sledge control can be preset by the user. ACCESS The access procedure is divided into two different modes, depending on the requested jump size (see Table 1).
OQ8868
The access procedure makes use of a track counting mechanism (see section "Off track counting"), a velocity signal based upon the number of tracks passed within a fixed time interval, a velocity setpoint calculated from the number of tracks to go and a user-programmable parameter indicating the maximum sledge performance. If the number of tracks to go is larger than break_dist, then the Sledge jump mode is activated; otherwise, the actuator jump is performed. The requested jump size, together with the required sledge braking distance at maximum access speed, defines the value break_dist. During the actuator jump mode, velocity control with a PI controller is used for the actuator. The sledge is then continuously controlled using the filtered value of the integrator contents of the actuator. All filter parameters (for actuator and sledge) are user-programmable. In the sledge jump mode, maximum power (user-programmable) is applied to the sledge in the correct direction, while the actuator becomes idle; the contents of the actuator integrator leaks to zero just after the sledge jump mode is initiated.
Table 1
Access modes JUMP SIZE 1 - break_distance(1) break distance(1) - 32768 ACCESS SPEED decreasing velocity maximum power to sledge(1)
ACCESS TYPE Actuator jump Sledge jump Note 1. Can be preset by the microcontroller.
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Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
RADIAL AUTOMATIC GAIN CONTROL LOOP The loop gain of the radial control loop can be corrected automatically to eliminate tolerances in the radial loop. This gain control injects a signal into the loop, which is used to correct the loop gain. Since this decreases the optimum performance, the gain control should only be activated briefly (e.g. when starting a new disc). This gain control differs from the `level initialization' previously mentioned. This level initialization should be performed first. The disadvantage of the level initialization without the gain control is that only tolerances from the front-end are reduced. Off track counting TPI is a flag that is used to indicate whether the spot is positioned on the track, with a margin of 14 of the track-pitch. In combination with the RP-flag (radial polarity; pin 35) the relative spot position over the tracks can be determined. These signals are affected by some uncertainties, caused by: * Disc defects, such as scratches and fingerprints * The high-frequency (HF) information on the disc, which is seen as noise by the detector signals. In order to determine the spot position with sufficient accuracy, extra conditions are necessary to generate a TL signal as well as an off track counter value. These extra conditions influence the maximum speed and this implies that one of the three following counting states is selected internally: * Protected state: used in normal play situations. In this state, a good protection against false detection caused by disc defects is important. * Slow counting state: used in low velocity track jump situations. In this state, a fast response is important, rather than the protection against disc defects. (If the phase relationship between TL and RP of a 12 rad is affected too much, the direction can no longer be determined accurately. * Fast counting state: used in high velocity track jump situations. The highest obtainable velocity is the most important feature in this state, in which counting on internally generated signals or on the Fast Track Count (FTC) input signal is possible. Defect detection
OQ8868
Because of the possible defects previously mentioned (fingerprints, etc.), a defect detection circuit is incorporated into the DSICS. Whenever this circuit detects a defect, it will hold all radial and focus controls. This circuit improves the playability of the application (black dot performance, etc.) and is programmable, to optimize it for specific disc defects. The actions of this circuit can be monitored on the DEFO pin (active HIGH). An external defect detection circuit can be added by removing the connection between DEFO and DEFI (normal operation) and connecting the external circuitry. These signals are affected by some uncertainties caused by: * Disc defects, such as scratches and fingerprints * The HF information on the disc, which is seen as noise by the detector signals. Off track detection During active radial tracking, off track detection is realized by continuously monitoring the off track counter value. The off track detector (OTD) flag becomes valid whenever the off track counter value is not equal to zero. Depending on the type of extended S-curve, the off track counter is reset after 34 extend or at the original track in the 214 track extend mode. Serial host Interface To control DSICS operation, a serial interface is implemented. This serial interface allows communication with a microcontroller via a 3-line or 2-line serial bus. In the 2 line, I2C-bus mode, it consists of: * Clock line SCL (SICL/SCL pin) * Data line SDA (SIDA/SDA pin). In the 3-line, TDA1301T-like mode, it consists of: * Clock line SICL (SICL/SCL pin) * Data line SIDA (SIDA/SDA pin) * Control line SILD. The SICL line is controlled by the microcontroller and can be completely asynchronous from the DSICS oscillator frequency. The SILD line is used for read/write control and end-of-byte signalling.
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Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
The communication is bi-directional and processes 8-bit words (byte, MSB first). The data present on SIDA is clocked with the positive edge of SICL. A single information exchange consists of one command byte and up to seven data bytes. The first byte defines the command, and is always input to the DSICS. This byte defines whether data has to be written to or read from the DSICS. If data has to be written to the DSICS, this byte also specifies the number of data bytes. The number of bytes read from the DSICS can vary from 0 to 128 and only depends on how many the microcontroller wants to read. Serial decoder interface The DSICS is able to control the decoder (SAA7345) through a second serial interface. If this connection is made, high-level features such as auto start-up and interrupt on subcode discontinuity can be used. In this case, the microcontroller has to communicate through the DSICS to the decoder. The interface to the decoder is a 3-line serial bus comprising the following signals: * Clock line (CDIC) * Data line (DA) * Control line (RAB). The serial bus is fully controlled by the DSICS, although it can be disabled by the microcontroller. Clock generation The DSICS should run internally with a clock of 8.4672 MHz. The circuit that generates the clock has three modes: the oscillator frequency divided by 2, 3 or 4 (software controlled). Therefore, it is possible to connect a crystal or a resonator with a frequency of 8.4672, 11.2896 or 16.9344 MHz. For the best performance, use of the 16.9344 MHz input frequency is recommended for 8x applications. For higher speeds the next clock frequencies are recommended: * 22.0147 MHz for 10 x CD-ROM data rate (8 x clock frequency +30%) * 25.4016 MHz for 12 x CD-ROM data rate (8 x clock frequency +50%) * 33.8688 MHz for 16 x CD-ROM data rate, including DVD (8 x clock frequency +100%)
OQ8868
These frequencies are derived from the currently popular decoder IC frequencies. It is also possible to drive the clock circuit with a TTL compatible external clock signal. The clock buffer output (CLKO) can supply the system clock or half the system clock (also switchable under software control via the serial bus) to be used as clock generator for other ICs. The oscillator circuit is optimized for low power dissipation, thus for applications beyond 8x the clock signal must be supplied external at pin XTALI. Reset Reset is controlled by means of the RSTI pin (active HIGH). This circuit ensures correct initialization of the digital circuit and the output stages. The minimum reset time is 250 ns. The inverse synchronized reset signal is available on the output pin RSTO. This signal can be used to reset the decoder and disable the SZA1010 (digital output stages) during a reset. Laser drive on The LDO pin is used to switch the laser drive off and on. It is an open drain output. When the laser is on, the output has a high impedance. This pin is automatically driven when the focus control loop is switched on.
1997 Feb 12
11
Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD VDDA VSS Pdiss Tstg Tamb Vesd HANDLING Electrostatic handling in accordance with "UZW-BO/FQ-0604". QUALITY SPECIFICATION In accordance with "SNW-FQ-611E". THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER from junction to ambient in free air VALUE 80 digital supply voltage analog supply voltage ground supply voltage difference between VSSA and VSSD power dissipation storage temperature operating ambient temperature electrostatic handling PARAMETER 0 0 -5 - 55 -40 -2000 MIN.
OQ8868
MAX. 6.5 6.5 +5 200 150 +85 +2000 V V
UNIT
mV mW C C V
UNIT K/W
1997 Feb 12
12
Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
CHARACTERISTICS VDDD = 5 V; VDDA = 5 V; VSSD = VSSA = 0 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supply VDDD VDDA IDDD IDDA IDD(q) Ptot Tamb Analog part DSICS ANALOG FRONT-END SPECIFICATION VDDA IDDA Iref Rext Vi II analog supply voltage analog supply current reference input current (XTLR) external resistor voltage on current input (XTLR) input current for pins D1 to D4 for pinsS1 and S2 Cext Vi VrefL VrefH (THD+N)/S S/N PSRR Gtol G cs Digital part DIGITAL INPUTS, WITH INTERNAL PULL-DOWN RESISTOR: TEST1, TEST2 AND DEFI VIL VIH Rpd LOW level input voltage HIGH level input voltage internal pull-down resistor to VSSD Tamb = -40 to +85 C Tamb = -40 to +85 C - 0.7VDDD 27 - - - external capacitors D1 to D4, S1, S2 voltage on current inputs D1 to D4, S1, S2 LOW level reference voltage HIGH level reference voltage total harmonic distortion plus noise-to-signal ratio signal-to-noise ratio power supply ripple rejection gain tolerance variance of gain between channels channel separation at VDDA; note 3 note 4 at 0 dB; note 2 note 1 note 1 3.871 1.935 100 - 0 0.5 - - - 13 - - - - 220 12 6 4.5 - 1.935 200 - - 5 - - 1.2 5.5 - 6 digital supply voltage analog supply voltage digital supply current analog supply current digital quiescent supply current total power dissipation operating ambient temperature 4.5 4.5 - - - - -40 - - 17 - - 115 - 5.5 5.5 - 9.0 10 - PARAMETER CONDITIONS MIN. TYP.
OQ8868
MAX.
UNIT
V V mA mA A mW C
+85
V mA A k V A A pF V V V dB dB dB % % dB
620 -
400
Virtual - VrefL 0 - -50 55 45 - - 60 0 2.5 -45 - - 18 2 -
0.3VDDD - 80
V V k
1997 Feb 12
13
Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
SYMBOL PARAMETER CONDITIONS Tamb = -40 to +85 C Tamb = -40 to +85 C - 2.0 27 Tamb = -40 to +85 C Tamb = -40 to +85 C - 0.7VDDD - Tamb = -40 to +85 C Tamb = -40 to +85 C - 2.4 27 - - - note 5 - - - - - - - - - - - - 2.0 4 4 - - - - MIN. TYP. - - - - - - - - - 4 0 - 27
OQ8868
MAX.
UNIT
DIGITAL INPUTS, WITH INTERNAL PULL-DOWN RESISTOR AND TTL COMPATIBLE: FTC VIL VIH Rpd VIL VIH ILI VIL VIH Rpd IOL IOH tr tf IOL IOH tr tf IOL IOH IOZ I tr tf VIL VIH IOL IOH IOZ I tr tf LOW level input voltage HIGH level input voltage internal pull-down resistor to VSSD LOW level input voltage HIGH level input voltage input leakage current 0.8 - 80 V V k
DIGITAL INPUTS: SILD, SICL AND ENIIC 0.3VDDD - 1 V V A V V k
DIGITAL INPUTS WITH INTERNAL PULL-DOWN RESISTOR, HYSTERESIS AND TTL COMPATIBLE: RSTI LOW level input voltage HIGH level input voltage internal pull-down resistor to VSSD LOW level output current HIGH level output current rise time fall time Vo = 0.4 V open drain 0.6 - 80 - - - - - - - - - - 5 - - - 0.8 - - - 5 - - -
DIGITAL OUTPUTS: LDO (OPEN DRAIN) mA mA ns ns
DIGITAL OUTPUTS: OTD, INTREQ, RAB, CL, RSTO, CLKO AND DEFO LOW level output current HIGH level output current rise time fall time Vo = 0.4 V Vo = VDDD - 0.4 V note 5 note 5 4 4 23 27 mA mA ns ns
DIGITAL OUTPUTS; 3-STATE: RA, FO, SL, RP, TL AND FOK LOW level output current HIGH level output current 3-state leakage current current rise time fall time Vo = 0.4 V Vo = VDDD - 0.4 V Tamb = -40 to +85 C Vo = 0 to VDDD note 5 note 5 Tamb = -40 to +85 C Tamb = -40 to +85 C Vo = 0.4 V Vo = VDDD - 0.4 V Tamb = -40 to +85 C Vo = 0 to VDDD note 5 note 5 4 4 - - 24 28 - - - - - - 19 33 mA mA A A ns ns
DIGITAL BIDIRECTIONAL: SIDA AND DA LOW level input voltage HIGH level input voltage LOW level output current HIGH level output current 3-state leakage current current rise time fall time V V mA mA A A ns ns
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Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
SYMBOL Oscillator fosc Cin Cfb Cout VIL VIH tH Notes 1. fsys = 8.4672 MHz; VrefL = 0 V. 2.4 2.4 a) For A/D converters D1 to D4: I I ( max ) = ---------- = ------------------ = 12 A 200 k R ext ------1.2 1.2 b) For A/D converters S1 and S2: I I ( max ) = ---------- = ------------------ = 6 A R ext 200 k 2. Measuring bandwidth: 200 Hz to 20 kHz; finADC = 1 kHz. 3. fripple = 1 kHz; Vripple = 0.5 V (p-p). 4. Gain tolerance is determined by the accuracy of external resistor Rext. 5. At 10 to 90% levels with CL = 50 pF; VDD = 4.5 V; Tj = 85 C. 6. The oscillator frequency specification is depending on the application speed (see Table 2). Table 2 Oscillator frequencies; note 1 TYPICAL OSCILLATOR FREQUENCY (MHz) 16.9344 22.0147 25.4016 33.8688 including DVD application REMARK oscillator frequency input capacitance feedback capacitance output capacitance note 6 8 - - - - 2.0 relative to clock period 45 - 8.5 3 2 - - - PARAMETER CONDITIONS MIN. TYP.
OQ8868
MAX.
UNIT
33.9 10 3.7 3
MHz pF pF pF
Slave clock mode LOW level input voltage HIGH level input voltage input HIGH time 0.5 - 55 V V %
APPLICATION SPEED 8x 10x 12x 16x Note
1. Note that the internal clock frequency is recommended as half of the oscillator frequency and that the digital power consumption scales with this clock frequency. For applications beyond 8x the clock signal must be supplied externally via pin XTALI.
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handbook, full pagewidth
1997 Feb 12
LEFT DAC RIGHT I2S AUDIO DECODER CD65 LO9585 DIGITAL SERVO IC DSICS OQ8868 MOTOR CONTROL CD-ROM DECODER
Philips Semiconductors
MECHANISM
APPLICATION INFORMATION
VDD
D1
D2
HF AMPLIFIER
D3
D4
OSDALAS2
D5
OQ8875
LASER HOST INTERFACE SCSI
MONITOR
Digital Servo Integrated Circuit Silent (DSICS)
A
FOCUS
DIGITAL POWER AMPLIFIER DSD3 SZA1010
B
TRACKING
16
ANALOG POWER AMPLIFIER TDA7072A SYSTEM CONTROLLER SERVO LO9585 S2B DATA PATH SYSTEM CONTROLLER DATA A = FOCUS ACTUATOR B = RADIAL ACTUATOR C = SLED MOTOR D = SPINDLE MOTOR E = HOME SWITCH
C
SLED BUFFER MANAGEMENT
D
MOTOR
E
HOME SWITCH
2-STAGE, 3-SPOTS CD-MECHANISM
MGE337
LOADER
Product specification
OQ8868
Fig.4 Application diagram.
Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
OQ8868
SOT307-2
c
y X
A 33 34 23 22 ZE
e Q E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 A1 (A 3) Lp L
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 Q 0.85 0.75 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1997 Feb 12
17
Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
OQ8868
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1997 Feb 12
18
Philips Semiconductors
Product specification
Digital Servo Integrated Circuit Silent (DSICS)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
OQ8868
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Feb 12
19
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547027/00/02/pp20
Date of release: 1997 Feb 12
Document order number:
9397 750 01655

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